View KV31P100M120SF8_8981896.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

kinetis kv31f 256 kb flash 120 mhz arm? cortex?-m4-based microcontroller with fpu the kv31 mcu family is a highly scalable member of the kinetis v series and provides a high-performance, cost-competitive motor control solution. built on the arm ? cortex ? -m4 core running at 120 mhz, combined with floating point and dsp capability, it delivers a highly capable platform enabling customers to build a highly scalable solution portfolio. additional features include: ? dual 16-bit adcs sampling at up to 1.2 ms/s in 12-bit mode ? 12 channels of highly flexible motor control timers (pwms) across 3 independent time bases ? large ram block enabling local execution of fast control loops at full clock speed ? enabled to support kinetis motor suite (kms), a bundled hardware and software solution that enables rapid configuration of bldc and pmsm motor drive systems performance ? 120 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz memories and memory interfaces ? 256 kb of embedded flash and 48 kb of ram ? preprogrammed kinetis flashloader for one-time, in- system factory programming system peripherals ? 16-channel dma controller ? independent external and software watchdog monitor clocks ? one crystal oscillator, two ranges: 32-40 khz or 3-32 mhz ? three internal oscillators: 32 khz, 4 mhz, and 48 mhz ? multi-purpose clock generator with pll and fll security and integrity modules ? hardware crc module ? 128-bit unique identification (id) number per chip ? hardware random-number generator ? flash access control to protect proprietary software human-machine interface analog modules ? two 16-bit sar adcs (1.2 ms/s in 12bit mode) ? one 12-bit dac ? two analog comparators (cmp) with 6- bit dac ? accurate internal voltage reference communication interfaces ? two spi modules ? three uart modules and one low-power uart ? two i2c modules: support for up to 1 mbps operation timers ? one 8-channel motor control/general purpose/ pwm timer ? two 2-channel motor control/general purpose timers with quadrature decoder functionality operating characteristics ? voltage range (including flash writes): 1.71 to 3.6 v ? temperature range (ambient): -40 to 105c kinetis motor suite ? supports velocity and position control of bldc & pmsm motors mkv31f256vll12 mkv31f256vlh12 mkv31f256vlh12p 100 lqfp (ll) 14 x 14 x 1.4 pitch 0.5 mm 64 lqfp (lh) 10 x 10 x 1.4 pitch 0.5 mm freescale semiconductor, inc. KV31P100M120SF8 data sheet: technical data rev. 7, 02/2016 ? 2014C2016 freescale semiconductor, inc. all rights reserved.
? up to 70 general-purpose i/o (gpio) ? implements field orient control (foc) using back emf to improve motor efficiency ? utilizes spintac control theory that improves overall system performance and reliability ordering information part number memory number of gpios flash (kb) sram (kb) mkv31f256vll12 256 48 70 mkv31f256vlh12 256 48 46 mkv31f256vlh12p 248 48 46 related resources type description resource selector guide the freescale solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector product selector product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. kv30fkv31fpb reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. KV31P100M120SF8rm data sheet the data sheet is this document. it includes electrical characteristics and signal connections. KV31P100M120SF8 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_ x n51m 1 kms user guide the kms user guide provides a comprehensive description of the features and functions of the kinetis motor suite solution. kinetis motor suite users guide (kms100ug) 2 kms api reference manual the kms api reference manual provides a comprehensive description of the api of the kinetis motor suite function blocks. kinetis motor suite api reference manual (kms100rm) 2 package drawing package dimensions are provided by part number: ? mkv31f256vll12 ? mkv31f256vlh12 ? mkv31f256vlh12p package drawing: ? 98ass23308w ? 98ass23234w ? 98ass23234w 1. to find the associated resource, go to freescale.com and perform a search using this term with the x replaced by the revision of the device you are using. 2. to find the associated resource, go to freescale.com and perform a search using document id figure 1 shows the functional modules in the chip. 2 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
memories and memory interfaces program (256 kb) ram crc programmable analog timers communication interfaces security and integrity clocks frequency- core debug interfaces dsp interrupt controller comparator x2 16-bit timer human-machine interface (hmi) up to system dma (16ch) low-leakage wakeup locked loop serial programming interface (ezport) reference internal clocks delay block timers interrupt periodic oscillators low/high frequency uart x3 ? cortex?-m4 arm fpu voltage ref phase- locked loop x2 i c 2 timers x1 (8ch) adc x2 spi x2 x1 lpuart high performance low-power 70 gpios (48 kb) flash internal watchdogs and external with 6-bit dac 12-bit dac x2 (2ch) 16-bit random- number generator flash access control figure 1. functional block diagram kinetis kv31f 256 kb flash, rev. 7, 02/2016 3 freescale semiconductor, inc.
table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 6 2.2.1 voltage and current operating requirements....... 6 2.2.2 lvd and por operating requirements................ 7 2.2.3 voltage and current operating behaviors............. 8 2.2.4 power mode transition operating behaviors........ 9 2.2.5 power consumption operating behaviors............ 10 2.2.6 emc radiated emissions operating behaviors..... 16 2.2.7 designing with radiated emissions in mind.......... 17 2.2.8 capacitance attributes......................................... 17 2.3 switching specifications................................................... 17 2.3.1 device clock specifications.................................. 17 2.3.2 general switching specifications......................... 18 2.4 thermal specifications..................................................... 18 2.4.1 thermal operating requirements......................... 19 2.4.2 thermal attributes................................................ 19 3 peripheral operating requirements and behaviors.................. 20 3.1 core modules.................................................................. 20 3.1.1 swd electricals .................................................. 20 3.1.2 jtag electricals.................................................. 21 3.2 system modules.............................................................. 24 3.3 clock modules................................................................. 24 3.3.1 mcg specifications.............................................. 24 3.3.2 irc48m specifications......................................... 27 3.3.3 oscillator electrical specifications........................ 27 3.4 memories and memory interfaces................................... 29 3.4.1 flash electrical specifications.............................. 29 3.4.2 ezport switching specifications........................... 31 3.5 security and integrity modules........................................ 32 3.6 analog............................................................................. 32 3.6.1 adc electrical specifications............................... 32 3.6.2 cmp and 6-bit dac electrical specifications....... 36 3.6.3 12-bit dac electrical characteristics.................... 39 3.6.4 voltage reference electrical specifications.......... 42 3.7 timers.............................................................................. 43 3.8 communication interfaces............................................... 43 3.8.1 dspi switching specifications (limited voltage range).................................................................. 44 3.8.2 dspi switching specifications (full voltage range).................................................................. 45 3.8.3 inter-integrated circuit interface (i2c) timing...... 47 3.8.4 uart switching specifications............................ 49 3.9 kinetis motor suite.......................................................... 49 4 dimensions............................................................................. 49 4.1 obtaining package dimensions....................................... 49 5 pinout...................................................................................... 50 5.1 kv31f signal multiplexing and pin assignments............ 50 5.2 recommended connection for unused analog and digital pins........................................................................ 54 5.3 kv31f pinouts................................................................. 55 6 part identification..................................................................... 57 6.1 description....................................................................... 57 6.2 format............................................................................. 58 6.3 fields............................................................................... 58 6.4 example........................................................................... 59 7 terminology and guidelines.................................................... 59 7.1 definitions........................................................................ 59 7.2 examples......................................................................... 59 7.3 typical-value conditions.................................................. 60 7.4 relationship between ratings and operating requirements.................................................................... 60 7.5 guidelines for ratings and operating requirements.......... 61 8 revision history...................................................................... 61 4 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings ratings kinetis kv31f 256 kb flash, rev. 7, 02/2016 5 freescale semiconductor, inc.
symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 158 ma v dio digital input voltage C0.3 v dd + 0.3 v v aio analog 1 C0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all digital pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v table continues on the next page... general 6 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio analog and i/o pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) -3 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection -25 ma v odpu open drain pullup voltage level v dd v dd v 2 v ram v dd voltage required to retain ram 1.2 v 1. all analog and i/o pins are internally clamped to v ss through esd protection diodes. if v in is less than v io_min or greater than v io_max , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v io_min -v in )/|i icio |. 2. open drain outputs must be pulled to vdd. 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 table continues on the next page... general kinetis kv31f 256 kb flash, rev. 7, 02/2016 7 freescale semiconductor, inc.
table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage 2.2.3 voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. typ. max. unit notes v oh output high voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -5 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -2.5 ma v dd C 0.5 v v oh output high voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -20 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -10 ma v dd C 0.5 v i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 5 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 v v ol output low voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 20 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 v v ol output low voltage reset_b table continues on the next page... general 8 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 3. voltage and current operating behaviors (continued) symbol description min. typ. max. unit notes 2.7 v v dd 3.6 v, i ol = 3 ma 0.5 v 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range all pins other than high drive port pins 0.002 0.5 a 1 , 2 high drive port pins 0.004 0.5 a i in input leakage current (total all pins) for full temperature range 1.0 a 2 r pu internal pullup resistors 20 50 k 3 r pd internal pulldown resistors 20 50 k 4 1. ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. measured at vdd=3.6v 3. measured at v dd supply voltage = v dd min and vinput = v ss 4. measured at v dd supply voltage = v dd min and vinput = v dd 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 80 mhz ? bus clock = 40 mhz ? flash clock = 20 mhz ? mcg mode: fei table 4. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls0 run 140 s ? vlls1 run 140 s ? vlls2 run 80 s table continues on the next page... general kinetis kv31f 256 kb flash, rev. 7, 02/2016 9 freescale semiconductor, inc.
table 4. power mode transition operating behaviors (continued) symbol description min. typ. max. unit notes ? vlls3 run 80 s ? lls2 run 6 s ? lls3 run 6 s ? vlps run 5.7 s ? stop run 5.7 s 1. normal boot (ftfa_opt[lpboot]=1) 2.2.5 power consumption operating behaviors the current parameters in the table below are derived from code executing a while(1) loop from flash, unless otherwise noted. the idd typical values represent the statistical mean at 25c, and the idd maximum values for run, wait, vlpr, and vlpw represent data collected at 125c junction temperature unless otherwise noted. the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 5. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_hsrun high speed run mode current - all peripheral clocks disabled, coremark benchmark code executing from flash @ 1.8v 25.66 26.35 ma 2 , 3 , 4 @ 3.0v 25.75 26.44 ma i dd_hsrun high speed run mode current - all peripheral clocks disabled, code executing from flash @ 1.8v 23.6 24.29 ma 2 @ 3.0v 23.7 24.39 ma i dd_hsrun high speed run mode current all peripheral clocks enabled, code executing from flash @ 1.8v 31.9 32.59 ma 5 @ 3.0v 32.0 32.69 ma table continues on the next page... general 10 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current in compute operation coremark benchmark code executing from flash @ 1.8v 15.8 16.49 ma 3 , 4 , 6 @ 3.0v 15.8 16.49 ma i dd_run run mode current in compute operation code executing from flash @ 1.8v 14.00 15.50 ma 6 @ 3.0v 14.00 15.69 ma i dd_run run mode current all peripheral clocks disabled, code executing from flash @ 1.8v 15.3 15.99 ma 7 @ 3.0v 15.4 16.09 ma i dd_run run mode current all peripheral clocks enabled, code executing from flash @ 1.8v 20.4 21.09 ma 8 @ 3.0v ? @ 25c 20.5 21.19 ma ? @ 70c 20.5 21.19 ma ? @ 85c 20.5 21.19 ma ? @ 105c 21.4 22.09 ma i dd_run run mode current compute operation, code executing from flash @ 1.8v 14.0 14.69 ma 9 @ 3.0v ? @ 25c 14.0 14.69 ma ? @ 70c 14.0 14.69 ma ? @ 85c 14.0 14.69 ma ? @ 105c 15.0 15.69 ma i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 8.1 8.79 ma 7 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 4.4 5.09 ma 10 i dd_vlpr very-low-power run mode current in compute operation coremark benchmark code executing from flash @ 1.8v 0.70 0.88 ma 3 , 4 , 11 @ 3.0v 0.70 0.88 ma i dd_vlpr very-low-power run mode current in compute operation, code executing from flash 0.61 0.79 table continues on the next page... general kinetis kv31f 256 kb flash, rev. 7, 02/2016 11 freescale semiconductor, inc.
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes @ 1.8v ma 11 @ 3.0v 0.61 0.79 ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 0.68 0.87 ma 12 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.10 1.28 ma 13 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.38 0.57 ma 14 i dd_stop stop mode current at 3.0 v @ -40c to 25c 0.27 0.35 ma @ 70c 0.32 0.47 ma @ 85c 0.32 0.51 ma @ 105c 0.45 0.77 ma i dd_vlps very-low-power stop mode current at 3.0 v @ -40c to 25c 4.5 12.00 a @ 70c 16.8 42.40 a @ 85c 28.9 73.45 a @ 105c 60.8 141.90 a i dd_lls3 low leakage stop mode 3 current at 3.0 v @ -40c to 25c 2.6 3.75 a @ 70c 6.6 12.00 a @ 85c 10.5 17.25 a @ 105c 21.0 40.70 a i dd_lls2 low leakage stop mode 2 current at 3.0 v @ -40c to 25c 2.4 3.40 a @ 70c 5.3 8.90 a @ 85c 5.1 10.05 a @ 105c 15.9 28.85 a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ -40c to 25c 1.9 2.30 a @ 70c 4.8 8.10 a @ 85c 7.6 11.30 a @ 105c 15.3 27.65 a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ -40c to 25c 1.7 2.10 a @ 70c 3.4 4.85 a @ 85c 5.1 8.80 a @ 105c 9.8 15.70 a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ -40c to 25c 0.71 0.96 a table continues on the next page... general 12 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes @ 70c 1.79 2.10 a @ 85c 2.9 4.70 a @ 105c 5.7 8.10 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled @ -40c to 25c 0.40 0.56 a @ 70c 1.39 1.70 a @ 85c 2.5 4.25 a @ 105c 5.3 7.50 a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled @ -40c to 25c 0.12 0.38 a @ 70c 1.05 1.38 a @ 85c 2.20 3.95 a @ 105c 4.9 7.10 a 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120mhz core and system clock, 60mhz bus clock, and 24mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. cache on and prefetch on, low compiler optimization. 4. coremark benchmark compiled using iar 7.2 with optimization level low. 5. 120mhz core and system clock, 60mhz bus clock, and 24mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. 6. 80 mhz core and system clock, 40 mhz bus clock, and 26.67 mhz flash clock. mcg configured for pee mode. compute operation. 7. 80mhz core and system clock, 40mhz bus clock, and 26.67mhz flash clock. mcg configured for fei mode. all peripheral clocks disabled. 8. 80mhz core and system clock, 40mhz bus clock, and 26.67mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled. 9. 80mhz core and system clock, 40mhz bus clock, and 26.67mhz flash clock. mcg configured for fei mode. compute operation. 10. 25mhz core and system clock, 25mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. 11. 4 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. compute operation. code executing from flash. 12. 4 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 13. 4 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 14. 4 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. general kinetis kv31f 256 kb flash, rev. 7, 02/2016 13 freescale semiconductor, inc.
table 6. low power mode peripheral adderstypical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls vlps stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i 48mirc 48 mhz internal reference clock 350 350 350 350 350 350 a i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) >oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 42 42 42 42 42 42 a general 14 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at frequencies between 50 mhz and 100mhz. mcg in pee mode at frequencies greater than 100 mhz. ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfa figure 3. run mode supply current vs. core frequency general kinetis kv31f 256 kb flash, rev. 7, 02/2016 15 freescale semiconductor, inc.
figure 4. vlpr mode supply current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 64 lqfp package parame ter conditions clocks frequency range level (typ.) unit notes v eme device configuration, test conditions and em testing per standard iec 61967-2. supply voltages: ? vdd = 3.3 v temp = 25c fsys = 120 mhz fbus = 60 mhz external crystal = 8 mhz 150 khzC50 mhz 14 dbuv 1 , 2 , 3 50 mhzC150 mhz 23 150 mhzC500 mhz 23 500 mhzC1000 mhz 9 iec level l 4 1. measurements were made per iec 61967-2 while the device was running typical application code. 2. measurements were performed on a similar 64lqfp device. 3. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. general 16 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
4. iec level maximums: m 18dbmv, l 24dbmv, k 30dbmv, i 36dbmv, h 42dbmv . 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes high speed run mode f sys system and core clock 120 mhz f bus bus clock 60 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system and core clock 80 mhz f bus bus clock 50 mhz f flash flash clock 26.67 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz table continues on the next page... general kinetis kv31f 256 kb flash, rev. 7, 02/2016 17 freescale semiconductor, inc.
table 9. device clock specifications (continued) symbol description min. max. unit notes f lptmr_pin lptmr clock 25 mhz f lptmr_erclk lptmr external reference clock 16 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, and timers. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) asynchronous path 50 ns 4 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 10 5 30 16 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater of synchronous and asynchronous timing must be met. 3. these pins have a passive filter enabled on the inputs. this is the shortest pulse width that is guaranteed to be recognized. 4. these pins do not have a passive filter on the inputs. this is the shortest pulse width that is guaranteed to be recognized. 5. 25 pf load general 18 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
2.4 thermal specifications 2.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja chip power dissipation. 2.4.2 thermal attributes board type symbol description 100 lqfp 64 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 61 67 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 48 48 c/w 2 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 51 55 c/w 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 42 42 c/w 3 r jb thermal resistance, junction to board 34 31 c/w 4 r jc thermal resistance, junction to case 16 16 c/w 5 table continues on the next page... general kinetis kv31f 256 kb flash, rev. 7, 02/2016 19 freescale semiconductor, inc.
board type symbol description 100 lqfp 64 lqfp unit notes jt thermal characterizatio n parameter, junction to package top outside center (natural convection) 3 3 c/w 6 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51-9 specification. 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). 3. determined according to jedec standard jesd51-6, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. 4. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 swd electricals table 12. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v s1 swd_clk frequency of operation ? serial wire debug 0 33 mhz s2 swd_clk cycle period 1/s1 ns s3 swd_clk clock pulse width ? serial wire debug 15 ns s4 swd_clk rise and fall times 3 ns s9 swd_dio input data setup time to swd_clk rise 8 ns s10 swd_dio input data hold time after swd_clk rise 1.4 ns s11 swd_clk high to swd_dio data valid 25 ns s12 swd_clk high to swd_dio high-z 5 ns peripheral operating requirements and behaviors 20 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
s2 s3 s3 s4 s4 swd_clk (input) figure 5. serial wire clock input timing s11 s12 s11 s9 s10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 6. serial wire data timing 3.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag 0 0 10 20 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width 50 ns table continues on the next page... peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 21 freescale semiconductor, inc.
table 13. jtag limited voltage range electricals (continued) symbol description min. max. unit ? boundary scan ? jtag and cjtag 25 ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 1 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 19 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag 0 0 10 15 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag 50 33 ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 1.4 ns j7 tclk low to boundary scan output data valid 27 ns j8 tclk low to boundary scan output high-z 27 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 26.2 ns j12 tclk low to tdo high-z 26.2 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns peripheral operating requirements and behaviors 22 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 23 freescale semiconductor, inc.
j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing j14 j13 tclk trst figure 10. trst timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules peripheral operating requirements and behaviors 24 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
3.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t total deviation of internal reference frequency (slow clock) over voltage and temperature +0.5/-0.7 2 % f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature +0.5/-0.7 2 %f dco 1 , 2 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.3 1.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_ft frequency deviation of internal reference clock (fast clock) over temperature and voltage factory trimmed at nominal vdd and 25 c +1/-2 5 %f intf_ft f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 71.99 mhz table continues on the next page... peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 25 freescale semiconductor, inc.
table 15. mcg specifications (continued) symbol description min. typ. max. unit notes 2197 f fll_ref high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f vco = 48 mhz ? f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 7 pll f vco vco operating frequency 48.0 120 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 8 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 8 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 9 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. 2.0 v <= vdd <= 3.6 v. 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. excludes any oscillator currents that are also consuming power while pll is in operation. 9. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. peripheral operating requirements and behaviors 26 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
3.3.2 irc48m specifications table 16. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 400 500 a f irc48m internal reference frequency 48 mhz f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over 0c to 70c 0.2 0.5 %f irc48m 1 f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over full temperature 0.4 1.0 %f irc48m 1 f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over full temperature 0.5 1.5 %f irc48m 1 j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 2 1. the maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean 3 sigma). 2. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by one of the following settings: ? mcg operating in an external clocking mode and mcg_c7[oscsel]=10 or mcg_c5[pllclken0]=1, or ? sim_sopt2[pllfllsel]=11 3.3.3 oscillator electrical specifications 3.3.3.1 oscillator dc electrical specifications table 17. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high-gain mode (hgo=1) 1 table continues on the next page... peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 27 freescale semiconductor, inc.
table 17. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low- power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x and c y can be provided by using either integrated capacitors or external components. 4. when low-power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other device. peripheral operating requirements and behaviors 28 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
3.3.3.2 oscillator frequency specifications table 18. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high-frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 29 freescale semiconductor, inc.
table 19. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 20. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec2k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 1.8 ms 1 t rdonce read once execution time 30 s 1 t pgmonce program once execution time 100 s t ersall erase all blocks execution time 175 1300 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 21. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 22. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash table continues on the next page... peripheral operating requirements and behaviors 30 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 22. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at C40 c t j 125 c. 3.4.2 ezport switching specifications table 23. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 25 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 31 freescale semiconductor, inc.
ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 11. ezport timing diagram 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog 3.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 24 and table 25 are achievable on the differential pins adcx_dpx, adcx_dmx. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit adc operating conditions table 24. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 table continues on the next page... peripheral operating requirements and behaviors 32 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 24. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 24.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20 1200 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37 461 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 33 freescale semiconductor, inc.
r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 12. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 25. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes 1.0 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors 34 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 25. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes 0.5 C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 35 freescale semiconductor, inc.
4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 13. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 14. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors 36 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
3.6.2 cmp and 6-bit dac electrical specifications table 26. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 37 freescale semiconductor, inc.
00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 15. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 38 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 16. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.3 12-bit dac electrical characteristics 3.6.3.1 12-bit dac operating requirements table 27. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 39 freescale semiconductor, inc.
3.6.3.2 12-bit dac operating behaviors table 28. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 330 a i dda_dach p supply current high-speed mode 1200 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors 40 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 17. typical inl error vs. digital code peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 41 freescale semiconductor, inc.
temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 18. offset at half scale vs. temperature 3.6.4 voltage reference electrical specifications table 29. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors 42 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 30. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1920 1.1950 1.1980 v 1 v out voltage reference output with user trim at nominal v dda and temperature=25c 1.1945 1.1950 1.1955 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) 15 mv 1 i bg bandgap only current 80 a i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 31. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 70 c table 32. vref limited-range operating behaviors symbol description min. max. unit notes v tdrift temperature drift (v max -v min across the limited temperature range) 10 mv 3.7 timers see general switching specifications . 3.8 communication interfaces peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 43 freescale semiconductor, inc.
3.8.1 dspi switching specifications (limited voltage range) the deserial serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the spi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 33. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid -2 ns ds7 dspi_sin to dspi_sck input setup 16.2 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 19. dspi classic spi timing master mode peripheral operating requirements and behaviors 44 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 34. slave mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 15 mhz 1 ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 21.4 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.6 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 17 ns ds16 dspi_ss inactive to dspi_sout not driven 17 ns 1. the maximum operating frequency is measured with noncontinuous cs and sck. when dspi is configured with continuous cs and sck, the spi clock must not be greater than 1/6 of the bus clock. for example, when the bus clock is 60 mhz, the spi clock must not be greater than 10 mhz. first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 20. dspi classic spi timing slave mode peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 45 freescale semiconductor, inc.
3.8.2 dspi switching specifications (full voltage range) the deserial serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the spi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 35. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -4.5 ns ds7 dspi_sin to dspi_sck input setup 24.6 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 21. dspi classic spi timing master mode peripheral operating requirements and behaviors 46 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 36. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 29.5 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 3.2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 25 ns ds16 dspi_ss inactive to dspi_sout not driven 25 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 22. dspi classic spi timing slave mode 3.8.3 inter-integrated circuit interface (i 2 c) timing table 37. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 1 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s table continues on the next page... peripheral operating requirements and behaviors kinetis kv31f 256 kb flash, rev. 7, 02/2016 47 freescale semiconductor, inc.
table 37. i 2 c timing (continued) characteristic symbol standard mode fast mode unit minimum maximum minimum maximum data hold time for i 2 c bus devices t hd ; dat 0 2 3.45 3 0 4 0.9 2 s data set-up time t su ; dat 250 5 100 3 , 6 ns rise time of sda and scl signals t r 1000 20 +0.1c b 7 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 6 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the maximum scl clock frequency in fast mode with maximum bus loading can only be achieved when using the high drive pins across the full voltage range and when using the normal drive pins and vdd 2.7 v. 2. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 3. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 4. input signal slew = 10 ns and output load = 50 pf 5. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. table 38. i 2 c 1 mbps timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b , 2 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbps can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. peripheral operating requirements and behaviors 48 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 23. timing definition for devices on the i 2 c bus 3.8.4 uart switching specifications see general switching specifications . 3.9 kinetis motor suite kinetis motor suite is a bundled software solution that enables the rapid configuration of motor drive systems, and accelerates development of the final motor drive application. several members of the kv3x family are enabled with kinetis motor suite. the enabled devices can be identified within the orderable part numbers in this table . for more information refer to kinetis motor suite user's guide (kms100ug) and kinetis motor suite api reference manual (kms100rm). note to find the associated resource, go to freescale.com and perform a search using document id. 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: dimensions kinetis kv31f 256 kb flash, rev. 7, 02/2016 49 freescale semiconductor, inc.
if you want the drawing for this package then use this document number 64-pin lqfp 98ass23234w 100-pin lqfp 98ass23308w 5 pinout 5.1 kv31f signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 100 lqfp 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 1 pte0/ clkout32k adc1_se4a adc1_se4a pte0/ clkout32k spi1_pcs1 uart1_tx i2c1_sda 2 2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx i2c1_scl spi1_sin 3 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_ cts_b 4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_ rts_b spi1_sout 5 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 lpuart0_ tx 6 pte5 disabled pte5 spi1_pcs2 lpuart0_ rx 7 pte6 disabled pte6 spi1_pcs3 lpuart0_ cts_b 8 3 vdd vdd vdd 9 4 vss vss vss 10 5 pte16 adc0_se4a adc0_se4a pte16 spi0_pcs0 uart2_tx ftm_clkin0 ftm0_flt3 11 6 pte17 adc0_se5a adc0_se5a pte17 spi0_sck uart2_rx ftm_clkin1 lptmr0_ alt3 12 7 pte18 adc0_se6a adc0_se6a pte18 spi0_sout uart2_ cts_b i2c0_sda 13 8 pte19 adc0_se7a adc0_se7a pte19 spi0_sin uart2_ rts_b i2c0_scl 14 adc0_dp1 adc0_dp1 adc0_dp1 15 adc0_dm1 adc0_dm1 adc0_dm1 16 adc1_dp1/ adc0_dp2 adc1_dp1/ adc0_dp2 adc1_dp1/ adc0_dp2 pinout 50 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
100 lqfp 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 17 adc1_dm1/ adc0_dm2 adc1_dm1/ adc0_dm2 adc1_dm1/ adc0_dm2 18 9 adc0_dp0/ adc1_dp3 adc0_dp0/ adc1_dp3 adc0_dp0/ adc1_dp3 19 10 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 20 11 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 21 12 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 22 13 vdda vdda vdda 23 14 vrefh vrefh vrefh 24 15 vrefl vrefl vrefl 25 16 vssa vssa vssa 26 17 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 27 18 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 28 19 cmp0_in4/ adc1_se23 cmp0_in4/ adc1_se23 cmp0_in4/ adc1_se23 29 vss vss vss 30 vdd vdd vdd 31 20 pte24 adc0_se17 adc0_se17 pte24 ftm0_ch0 i2c0_scl ewm_out_ b 32 21 pte25 adc0_se18 adc0_se18 pte25 ftm0_ch1 i2c0_sda ewm_in 33 pte26/ clkout32k disabled pte26/ clkout32k 34 22 pta0 jtag_tclk/ swd_clk/ ezp_clk pta0 uart0_ cts_b ftm0_ch5 ewm_in jtag_tclk/ swd_clk ezp_clk 35 23 pta1 jtag_tdi/ ezp_di pta1 uart0_rx ftm0_ch6 cmp0_out ftm2_qd_ pha ftm1_ch1 jtag_tdi ezp_di 36 24 pta2 jtag_tdo/ trace_ swo/ ezp_do pta2 uart0_tx ftm0_ch7 cmp1_out ftm2_qd_ phb ftm1_ch0 jtag_tdo/ trace_ swo ezp_do 37 25 pta3 jtag_tms/ swd_dio pta3 uart0_ rts_b ftm0_ch0 ftm2_flt0 ewm_out_ b jtag_tms/ swd_dio 38 26 pta4/ llwu_p3 nmi_b/ ezp_cs_b pta4/ llwu_p3 ftm0_ch1 ftm0_flt3 nmi_b ezp_cs_b 39 27 pta5 disabled pta5 ftm0_ch2 jtag_ trst_b 40 vdd vdd vdd pinout kinetis kv31f 256 kb flash, rev. 7, 02/2016 51 freescale semiconductor, inc.
100 lqfp 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 41 vss vss vss 42 28 pta12 disabled pta12 ftm1_ch0 ftm1_qd_ pha 43 29 pta13/ llwu_p4 disabled pta13/ llwu_p4 ftm1_ch1 ftm1_qd_ phb 44 pta14 disabled pta14 spi0_pcs0 uart0_tx 45 pta15 disabled pta15 spi0_sck uart0_rx 46 pta16 disabled pta16 spi0_sout uart0_ cts_b 47 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_ rts_b 48 30 vdd vdd vdd 49 31 vss vss vss 50 32 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 51 33 pta19 xtal0 xtal0 pta19 ftm0_flt0 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 52 34 reset_b reset_b reset_b 53 35 ptb0/ llwu_p5 adc0_se8/ adc1_se8 adc0_se8/ adc1_se8 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha uart0_rx 54 36 ptb1 adc0_se9/ adc1_se9 adc0_se9/ adc1_se9 ptb1 i2c0_sda ftm1_ch1 ftm0_flt2 ewm_in ftm1_qd_ phb uart0_tx 55 37 ptb2 adc0_se12 adc0_se12 ptb2 i2c0_scl uart0_ rts_b ftm0_flt1 ftm0_flt3 56 38 ptb3 adc0_se13 adc0_se13 ptb3 i2c0_sda uart0_ cts_b ftm0_flt0 57 ptb9 disabled ptb9 spi1_pcs1 lpuart0_ cts_b 58 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 lpuart0_ rx ftm0_flt1 59 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck lpuart0_ tx ftm0_flt2 60 vss vss vss 61 vdd vdd vdd 62 39 ptb16 disabled ptb16 spi1_sout uart0_rx ftm_clkin0 ewm_in 63 40 ptb17 disabled ptb17 spi1_sin uart0_tx ftm_clkin1 ewm_out_ b 64 41 ptb18 disabled ptb18 ftm2_ch0 ftm2_qd_ pha 65 42 ptb19 disabled ptb19 ftm2_ch1 ftm2_qd_ phb 66 ptb20 disabled ptb20 cmp0_out 67 ptb21 disabled ptb21 cmp1_out 68 ptb22 disabled ptb22 69 ptb23 disabled ptb23 spi0_pcs5 pinout 52 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
100 lqfp 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 70 43 ptc0 adc0_se14 adc0_se14 ptc0 spi0_pcs4 pdb0_ extrg ftm0_flt1 spi0_pcs0 71 44 ptc1/ llwu_p6 adc0_se15 adc0_se15 ptc1/ llwu_p6 spi0_pcs3 uart1_ rts_b ftm0_ch0 lpuart0_ rts_b 72 45 ptc2 adc0_se4b/ cmp1_in0 adc0_se4b/ cmp1_in0 ptc2 spi0_pcs2 uart1_ cts_b ftm0_ch1 lpuart0_ cts_b 73 46 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout lpuart0_ rx 74 47 vss vss vss 75 48 vdd vdd vdd 76 49 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out lpuart0_ tx 77 50 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 cmp0_out ftm0_ch2 78 51 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_ extrg i2c0_scl 79 52 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin i2c0_sda 80 53 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 81 54 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 ftm2_flt0 82 55 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl 83 56 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda 84 ptc12 disabled ptc12 85 ptc13 disabled ptc13 86 ptc14 disabled ptc14 87 ptc15 disabled ptc15 88 vss vss vss 89 vdd vdd vdd 90 ptc16 disabled ptc16 lpuart0_ rx 91 ptc17 disabled ptc17 lpuart0_ tx 92 ptc18 disabled ptc18 lpuart0_ rts_b 93 57 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_ rts_b ftm0_ch0 lpuart0_ rts_b 94 58 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_ cts_b ftm0_ch1 lpuart0_ cts_b 95 59 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm0_ch2 lpuart0_ rx i2c0_scl 96 60 ptd3 disabled ptd3 spi0_sin uart2_tx ftm0_ch3 lpuart0_ tx i2c0_sda pinout kinetis kv31f 256 kb flash, rev. 7, 02/2016 53 freescale semiconductor, inc.
100 lqfp 64 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 97 61 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_ rts_b ftm0_ch4 ewm_in spi1_pcs0 98 62 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_ cts_b ftm0_ch5 ewm_out_ b spi1_sck 99 63 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 ftm0_flt0 spi1_sout 100 64 ptd7 disabled ptd7 uart0_tx ftm0_ch7 ftm0_flt1 spi1_sin 5.2 recommended connection for unused analog and digital pins the following table shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application. table 39. recommended connection for unused analog interfaces pin type short recommendation detailed recommendation analog/non gpio pgax/adcx float analog input - float analog/non gpio adcx/cmpx float analog input - float analog/non gpio vref_out float analog output - float analog/non gpio dacx_out float analog output - float analog/non gpio rtc_wakeup_b float analog output - float analog/non gpio xtal32 float analog output - float analog/non gpio extal32 float analog input - float gpio/analog pta18/extal0 float analog input - float gpio/analog pta19/xtal0 float analog output - float gpio/analog ptx/adcx float float (default is analog input) gpio/analog ptx/cmpx float float (default is analog input) gpio/digital pta0/jtag_tclk float float (default is jtag with pulldown) gpio/digital pta1/jtag_tdi float float (default is jtag with pullup) gpio/digital pta2/jtag_tdo float float (default is jtag with pullup) gpio/digital pta3/jtag_tms float float (default is jtag with pullup) gpio/digital pta4/nmi_b 10k? pullup or disable and float pull high or disable in pcr & fopt and float gpio/digital ptx float float (default is disabled) vdda vdda always connect to vdd potential always connect to vdd potential table continues on the next page... pinout 54 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 39. recommended connection for unused analog interfaces (continued) pin type short recommendation detailed recommendation vrefh vrefh always connect to vdd potential always connect to vdd potential vrefl vrefl always connect to vss potential always connect to vss potential vssa vssa always connect to vss potential always connect to vss potential 5.3 kv31f pinouts the following figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout kinetis kv31f 256 kb flash, rev. 7, 02/2016 55 freescale semiconductor, inc.
pte24 cmp0_in4/adc1_se23 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 vssa vrefl vrefh vdda adc1_dm0/adc0_dm3 adc1_dp0/adc0_dp3 adc0_dm0/adc1_dm3 adc0_dp0/adc1_dp3 pte19 pte18 pte17 pte16 vss vdd pte1/llwu_p0 pte0/clkout32k 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc11/llwu_p11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb19 ptb18 ptb17 ptb16 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 pta18 vss vdd pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte25 figure 24. kv31f 64 lqfp pinout diagram (top view) pinout 56 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 adc1_dp0/adc0_dp3 adc0_dm0/adc1_dm3 adc0_dp0/adc1_dp3 adc1_dm1/adc0_dm2 adc1_dp1/adc0_dp2 adc0_dm1 adc0_dp1 pte19 pte18 pte17 pte16 vss vdd pte6 pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0/clkout32k 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda adc1_dm0/adc0_dm3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6/llwu_p15 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte26/clkout32k pte25 pte24 vdd vss cmp0_in4/adc1_se23 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 98 ptd5 97 ptd4/llwu_p14 96 ptd3 95 ptd2/llwu_p13 94 ptd1 93 ptd0/llwu_p12 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11/llwu_p11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 25. kv31f 100 lqfp pinout diagram (top view) 6 part identification part identification kinetis kv31f 256 kb flash, rev. 7, 02/2016 57 freescale semiconductor, inc.
6.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 6.2 format part numbers for this device have the following format: q kv## a fff r t pp cc s n 6.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kv## kinetis v series ? kv3x: cortex-m4 based mcu a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu fff program flash memory size ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 xfbga (8 mm x 8 mm) ? dc = 121 xfbga (8 mm x 8 mm x 0.5 mm) cc maximum cpu frequency (mhz) ? 10 = 100 mhz ? 12 = 120 mhz s software type ? p = kms-pmsm and bldc ? (blank) = not software enabled n packaging type ? r = tape and reel ? (blank) = trays part identification 58 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
6.4 example this is an example part number: mkv31f256vll12p 7 terminology and guidelines 7.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. terminology and guidelines kinetis kv31f 256 kb flash, rev. 7, 02/2016 59 freescale semiconductor, inc.
7.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example 7.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v terminology and guidelines 60 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
7.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 7.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8 revision history the following table provides a revision history for this document. table 40. revision history rev. no. date substantial changes 7 02/2016 ? added terminology and guideline section ? updated front matter section ? added kms related information in front matter ? added kinetis motor suite section ? added "s" in format and part identification table table continues on the next page... revision history kinetis kv31f 256 kb flash, rev. 7, 02/2016 61 freescale semiconductor, inc.
table 40. revision history (continued) rev. no. date substantial changes ? updated the part number example ? updated irc48m specifications table 6 10/2015 ? in "power consumption operating behaviors" section, added "low power mode peripheral adderstypical value" table ? in "thermal operating requirements" table, in footnote, corrected "t j = t a + ja " to "t j = t a + r ja " ? updated "irc48m specifications" table ? updated "nvm program/erase timing specifications" table; updated values for t hversall (erase all high-voltage time) ? in "slave mode dspi timing (limited voltage range)" table, added footnote regarding maximum frequency of operation ? added new section, "recommended connections for unused analog and digital pins" 5 4/2015 ? throughout: removed notes stating that the 64-pin mapbga package for this product is not yet available ? on page 1: ? under "security and integrity modules" added "hardware random-number generator" ? under "communication interfaces," updated i 2 c bullet to indicate support for up to 1 mbps operation ? under "operating characteristics," specified that voltage range includes flash writes ? in figure, "functional block diagram," added "random-number generator" and "flash access control" ? in "voltage and current operating requirements" table: ? removed content related to positive injection ? updated footnote 1 to say that all analog and i/o pins are internally clamped to v ss only (not v ss and v dd )through esd protection diodes. ? in "power consumption operating behaviors" table: ? added additional temperature data in power consumption table ? added max idd values based on characterization results equivalent to mean + 3 sigma ? updated "emc radiated emissions operating behaviors" table ? in "thermal operating requirements" table, added the following footnote for ambient temperature: "maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + ja x chip power dissipation" ? updated "irc48m specifications": ? updated maximum values for firc48m_lv and firc48m_hv (full temperature) ? added specifications for firc48m_hv (-40c to 85c) ? in "i 2 c timing" table, ? added the following footnote on maximum fast mode value for scl clock frequency: "the maximum scl clock frequency in fast mode with maximum bus loading can only be achieved when using the high drive pins across the full voltage range and when using the normal drive pins and vdd 2.7 v." ? updated minimum fast mode value for low period of the scl clock to 1.25 ? added "i 2 c 1 mbps timing" table ? specified that the figure, "kv31f 64 lqfp pinout diagram" is a top view ? specified that the figure, "kv31f 100 lqfp pinout diagram" is a top view ? removed section 6, "ordering parts." 4 7/2014 ? in "power consumption operating behaviors table": table continues on the next page... revision history 62 kinetis kv31f 256 kb flash, rev. 7, 02/2016 freescale semiconductor, inc.
table 40. revision history (continued) rev. no. date substantial changes ? updated existing typical power measurements ? added new typical power measurements for the following: ? idd_hsrun (high speed run mode current executing coremark code) ? idd_runco (run mode current in compute operation, executing coremark code) ? idd_run (run mode current in compute operation, executing while(1) loop) ? idd_vlpr (very low power mode current executing coremark code) ? idd_vlpr (very low power run mode current in compute operation, executing while(1) loop) 3 7/2014 ? on p. 1: ? updated introduction ? under "memories and memory interfaces," added bullet, "pre-programmed kinetis flashloader for one-time, in-system factory programming" ? under "security and integrity modules," added bullet, "hardware random- number generator" ? in "voltage and current operating ratings" table, updated maximum digital supply current ? updated "voltage and current operating behaviors" table ? updated "power mode transition operating behaviors" table ? updated "power consumption operating behaviors" table ? updated figure, "run mode current vs core frequency" ? updated figure, "very low power run (vlpr) current vs core frequency" ? updated "emc radiated emissions operating behaviors for 64 lqfp package" table ? updated "thermal attributes" table ? updated "mcg specifications" table ? updated "irc48m specifications" table ? updated "16-bit adc operating conditions" table ? updated "voltage reference electrical specifications" section 2 3/2014 initial public release revision history kinetis kv31f 256 kb flash, rev. 7, 02/2016 63 freescale semiconductor, inc.
how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale, the freescale logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm, arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. spintac is a trademark of linestream technologies, inc. all rights reserved. ? 2014C2016 freescale semiconductor, inc. document number KV31P100M120SF8 revision 7, 02/2016

▲Up To Search▲

Price & Availability of KV31P100M120SF8

	To Download KV31P100M120SF8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .